The present invention relates to a method for manufacturing a semiconductor device and more particularly for manufacturing a transistor having a high density LDD (Lightly Doped Drain) structure.
A prior art method for manufacturing a transistor in connection with these kinds of semiconductor devices is exemplified in "Electron Device (1982) vol. ED-209, No. 4, Pages 590-596". FIGS. 2(a).about.(e) show sectional views corresponding to process steps of the prior art method disclosed in the above reference.
First, a field oxide film 2 and a gate oxide film 3 are formed by deposition on a predetermined area of a P-type silicon substrate 1 (hereinafter simply called a substrate) selectively and respectively. Thereafter, a phosphorus doped polysilicon layer 4 and a refractory metal silicide layer 5 such as WSi.sub.2 and MoSi.sub.2 are deposited consecutively on the gate oxide layer 3 so as to form a polycide gate electrode layer.
Then, N.sup.- layers 6 for sourse and drain regions are formed in the substrate 1 by ion-implanting.
Moreover, a silicon oxide film 7 is deposited by a CVD (Chemical Vapour Deposition) process all over the surface of the substrate 1 containing the field oxide film 2 and the polycide gate electrode layers 4 and 5. Then, the silicon oxide film 7 is selectively etched by RIE (Reactive Ion Etching) such a manner that the silicon oxide film 7 is preserved on the sidewall of the polycide gate electrode layers as a sidewall spacer insulating film 7a.
Then, after forming an N.sup.+ layer 8 is formed by ion implanting arsenic (As) impurities at a high concentration into the substrate 1, an intermediate insulating layer for example (BPSG film) 9, a contact region 10 and an aluminum interconnection layer 11 are consecutively formed pursuant to a well-known process technology to manufacture an N-type channel transistor.
According to the above-mentioned prior art method, hot carriers generated beneath the sidewall spacer insulating film 7a can be trapped by the gate oxide film 3 because the sidewall spacer insulating film 7a does not constitute a gate electrode, thereby causing resistance increase of the N.sup.- layer 6 at the beginning of operational test to induce the mutual conductance, gm, aggravation. In addition, there is a problem that an offset gate can be easily generated in the case of P-type channel transistors. There is also another problem that in the case of forming the side wall spacer insulating film 7a of RIE of the silicon oxide film 7, the field oxide film 2 is reduced in thickness due to overetching, thereby aggravating the element isolation characteristic.